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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
www.maxim-ic.com
GENERAL DESCRIPTION
The DS2155/DS2156 design kits are evaluation boards for the DS2155 and DS2156. The DS2155/DS2156 design kits are intended to be used as daughter cards with either the DK2000 or the DK101 motherboards. The boards are complete with a single-chip transceiver (SCT), transformers, termination resistors, configuration switches, line protection circuitry, network connectors, and an interface to the motherboard.
FEATURES
Expedites New Designs by Eliminating FirstPass Prototyping Interfaces Directly to the DK101 or DK2000 Motherboards Demonstrates Key Functions of the DS2156 and DS2155 High-Level Software Provides Visual Access to Registers Software-Controlled (Register Mapped) Configuration Switches to Facilitate Clock and Signal Routing BNC Connections for 75 E1 Bantam and RJ48 Connectors for 120 E1 and 100 T1 Multitap Transformer to Facilitate True Impedance Matching for 75 and 120/100 Paths Network Interface Protection for Overvoltage and Overcurrent Events UTOPIA II Bus Connection for MPC8260 (DS2156 Only) UTOPIA II Prototype Connectors (DS2156 Only) Test Points and Prototype Area Available for Further Customization
ORDERING INFORMATION
PART DS2155DK DS2156DK DESCRIPTION DS2155 Design Kit Daughter Card DS2156 Design Kit Daughter Card
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
TABLE OF CONTENTS
COMPONENT LIST.....................................................................................................................3 BASIC OPERATION....................................................................................................................4
HARDWARE CONFIGURATION .................................................................................................................. 4 QUICK SETUP (DEMO MODE) .................................................................................................................. 4 QUICK SETUP (REGISTER VIEW) ............................................................................................................. 4 SAMPLE UTOPIA II CONFIGURATION (DS2156 ONLY)............................................................................. 5
REGISTER MAP..........................................................................................................................5
CPLD REGISTER MAP ........................................................................................................................... 6
DS2155/DS2156 INFORMATION................................................................................................8 DS2155DK/DS2156DK INFORMATION......................................................................................8 TECHNICAL SUPPORT ..............................................................................................................8 SCHEMATICS .............................................................................................................................8
LIST OF TABLES
Table 1. Daughter Card Address Map .........................................................................................5 Table 2. CPLD Register Map .......................................................................................................6
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
COMPONENT LIST
DESIGNATION C1-C5, C8-C12, C15-C19, C21, C22, C29-C34 C7, C36 C13, C14 C23 C24-C27 C35 DS1, DS4-DS18 DS2, DS3 F1-F6 J1, J2 J3, J4 J5, J6 J7-J9 JT10 L1 R1, R14, R21 R2, R3, R58, R59 R4, R5, R60 R6, R9, R10, R13, R15-R19, R22, R23, R25-R29, R32, R37, R38, R44, R47-R49, R61 R7, R8, R11, R12, R30, R31, R35, R36, R39-R43, R45, R50-R53 R24 R33, R34 R46 R54, R55 R56, R57 RJ1 SW1 T1 U11 U1-U4, U6 U5 U7-U10 Z1, Z6-Z8 Z2, Z3 Z4, Z5 Z9, Z10 QTY 23 2 2 1 4 1 16 2 6 2 2 2 3 1 1 3 4 3 24 DESCRIPTION 0.1mF 10%, 16V ceramic capacitors (0603) 1mF 10%, 16V ceramic capacitors (1206) 0.1mF 10%, 16V ceramic capacitors (0805) 0.1mF 10%, 25V ceramic capacitor (1206) 0.22mF, 50V ceramic capacitors 10mF 20%, 16V tantalum capacitor (B case) LED, green, SMD LED, red, SMD 250V, 1.25A fuse, SMT Male 0.1, SMD, 50-pin, dual-row vertical Bantam connectors Connector BNC RA 5-pin Socket, SMD, 50-pin, dual-row vertical Connector, 10-pin, dual-row vertical Choke, dual 4-line 24mH, 8-pin SO 51.1W 1%, 1/8W resistors (1206) 0W 5%, 1/8W resistors (1206) 51.1W 1%, 1/10W resistors (0805) 10kW 1%, 1/10W resistors (0805) SUPPLIER Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Digi-Key Teccor Electronics Samtec SWK Kruvand Samtec Digi-Key Pulse Engineering Digi-Key Digi-Key Digi-Key Digi-Key PART 311-1088-1-ND PCC1882CT-ND 311-1142-1-ND PCC1883CT-ND UNK PCS3106CT-ND P501CT-ND P500CT-ND F1250T TSM-125-01-T-DV RTT34B02 UCBJR220 TFM-125-02-S-DLC S2012-05-ND PE-65857 P51.1FCT-ND P0.0ETR-ND P51.1CCT-ND P10.0KCCT-ND
18 1 2 1 2 2 1 1 1 1 5 1 4 4 2 2 2
330W 0.1%, 1/10W MF resistors (0805) 1.0kW 1%, 1/10W resistor (0805) NOPOP 4.7kW 1%, 1/8W resistor (0805) 61.9W 1%, 1/8W resistors (1206) 49.9W 1%, 1/8W resistors (1206) RJ48 connector Switch DPDT slide 6-pin TH XFMR 16-pin SMT T1/E1/J1 XCVR 100-pin QFP, 0C to +70C BBUS switch 10-bit CMOS, 150-mil, 24-pin SO 144-pin macrocell CPLD Quad bus switch, 150-mil, 16-pin SO 160V, 500A Sidactor 58V, 500A Sidactor 6V, 50A Sidactor 25V, 500A Sidactor
Digi-Key Digi-Key -- Digi-Key Digi-Key Digi-Key Molex Avnet Pulse Engineering Dallas Semiconductor IDT Avnet IDT Teccor Electronics Teccor Electronics Teccor Electronics Teccor Electronics
P330ZCT-ND P1.00KCCT-ND NOPOP 9C08052A4701FK HFT P61.9FCT-ND P49.9FCT-ND 43223 SSA22 TX1099 DS2156L IDTQS3R861Q XC95144XL10TQ100C IDTQS3125Q P1800SCMC P0640SCMC P0080SAMC P0300SCMC
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
BASIC OPERATION
This design kit relies upon several supporting files, which can be downloaded from our website at www.maximic.com/DS2155DK.
Hardware Configuration
Using the DK101 processor board: * Connect the daughter card to the DK101 processor board. * Supply 3.3V to the banana-plug receptacles marked GND and VCC_3.3V. (The external 5V connector and the TIM 5V supply headers are unused.) * All processor board DIP switch settings should be in the ON position with exception for the flash programming switch, which should be OFF. * From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs(R)ChipView(R)ChipView. Using the DK2000 processor board: * Connect the daughter card to the DK2000 processor board. * Connect J1 to the power supply that is delivered with the kit. Alternately, a PC power supply can be connected to connector J2. * From the Programs menu launch the host application named ChipView.exe. Run the ChipView application. If the default installation options were used, click the Start button on the Windows toolbar and select Programs(R)ChipView(R)ChipView. General: * Upon power-up the RLOS LED is lit, as well as the MCLK-2.048MHz and TCLK-2.048MHz LEDs. * Due to the dual winding transformer, only the 120W line build-out configuration setting is needed to cover 75W E1 and 120W E1.
Quick Setup (Demo Mode)
* * * The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Demo Mode. The program requests a configuration file, then select between the displayed files. (DS2155_E1_DSNCOM_DRVR.cfg or DS2155_T1_DSNCOM_DRVR.cfg). The Demo Mode screen appears. Upon external loopback, the LOS and OOF indicators extinguish.
Quick Setup (Register View)
* * * * The PC loads the program, offering a choice among Demo Mode, Register View, and Terminal Mode. Select Register View. The program requests a definition file, then select DS2155.def. The Register View screen appears, showing the register names, acronyms, and values. Predefined register settings for several functions are available as initialization files. 3/4 INI files are loaded by selecting the menu File(R)Reg Ini File(R)Load Ini File. 3/4 Load the INI file DS2155_T1_BERT_ESF.ini. 3/4 After loading the INI file the following may be observed: The RLOS LED extinguishes upon external loopback. The DS2155/DS2156 begins transmitting a Daly pattern. When external loopback is applied, the BERT bit-count registers BBC1-3 and BEC1-3 may be updated by clearing and setting BC1.LC and clicking the Read All button.
Miscellaneous: * Clock frequencies and certain pin bias levels are provided by a register-mapped CPLD, which is on the DS2155/DS2156 daughter card. * The definition file for this CPLD is named DS215x_35x_CPLD_V2.def. See the CPLD Register Map section for definitions. * All files referenced above are available for download at www.maxim-ic.com/DS2155DK. 4 of 21
DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
Sample UTOPIA II Configuration (DS2156 Only)
The following register settings configure the DS2156 daughter card for UTOPIA II, single CLAV, 8-bit mode on PHY port 0. UTOPIA II bus connection is provided by header J1 (Tx) and header J2 (Rx). After configuring the following registers toggle the MSTREG.URST bit to reset the UTOPIA II core. UTOPIA II Setup, Register Settings for daughter card CPLD
NAME SWITCH 1 SWITCH 2 SWITCH 3 VALUE 0x0F 0x03 0x0F NAME SWITCH 4 LEVELS VALUE 0x0F 0x07
UTOPIA II Setup, Register Settings for DS2156 E1 Configuration
NAME MSTREG E1RCR1 E1RCR2 E1TCR1 E1TCR2 CCR1 CCR4 IOCR1 IOCR2 VALUE 0x02 0x68 0x00 0x15 0x00 0x00 0x00 0x00 0x00 NAME LBCR TAF TNAF LIC1 LIC2 LIC3 LIC4 VALUE 0x00 0x9B 0xC0 0x11 0x90 0x00 0x00
UTOPIA II Setup, Register Settings for DS2156 UTOPIA II Configuration
NAME U_TCFR U_TCR1 U_TCR2 U_RCFR U_RCR1 VALUE 0x01 0x05 0x00 0x01 0x01 NAME U_RCR2 U_TIUPB PCPR PCDR1, 2, 3, 4 VALUE 0x0 0x0 0x22 0x0
REGISTER MAP
The DK101 daughter card address space begins at 0x81000000. The DK2000 daughter card address space begins at: 0x30000000 for slot 0 0x40000000 for slot 1 0x50000000 for slot 2 0x60000000 for slot 3 All offsets given in Table 1 are relative to the beginning of the daughter card address space.
Table 1. Daughter Card Address Map
OFFSET 0X0000 to 0X0015 0X1000 to 0X10ff DEVICE CPLD Single-Chip Transceiver DESCRIPTION Board identification and clock/signal routing Board is populated with one of the following: DS2156, DS2155, DS21352, or DS21354. Please see data sheet for details.
Registers in the CPLD can be easily modified using the ChipView.exe, a host-based user interface software along with the definition file named DS215x_35x_CPLD_V2.def. Definition files for the SCT are named DS2155.def, DS21352.def, or DS21354.def, depending on the board population option.
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
CPLD Register Map Table 2. CPLD Register Map
OFFSET 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 0X0011 0X0012 0X0013 0X0014 0X0015 NAME BID XBIDH XBIDM XBIDL BREV AREV PREV SWITCH1 SWITCH2 SWITCH3 SWITCH4 LEVELS TYPE Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Write Read-Write Read-Write Read-Write Read-Write DESCRIPTION Board ID High-Nibble Extended Board ID Middle-Nibble Extended Board ID Low-Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision Pin to 1.544MHz Pin to 2.048MHz Pin-to-Pin Connect Pin-to-Pin Connect Set Level On Pin 1 = 3.3V
ID Registers
OFFSET 0X0000 0X0002 0X0003 0X0004 0X0005 0X0006 0X0007 NAME BID XBIDH XBIDM XBIDL BREV AREV PREV TYPE Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only Read-Only VALUE DESCRIPTION
0xD 0x0 0x0 0x5 Displays current FAB revision Displays current assembly revision Displays current PLD firmware revision
Board ID
High-Nibble Extended Board ID Middle-Nibble Extended Board ID Low-Nibble Extended Board ID Board FAB Revision Board Assembly Revision PLD Revision
Control Registers
The control registers are used primarily to control several banks of FET switches that route clocks and backplane signals. Please note that certain register settings cause line contention, e.g., setting SWITCH1.4 and SWITCH2.4 both to 0 would drive MCLK with both 1.544MHz and 2.048MHz. SWITCH1: PIN TO 1.544MHz (OFFSET = 0x0011) INITIAL VALUE = 0xF (MSB) -- NAME MCLK TCLK RSYSCLK TSYSCLK (LSB) TSYSCLK
--
--
--
MCLK
TCLK
RSYSCLK
POSITION SWITCH1.3 SWITCH1.2 SWITCH1.1 SWITCH1.0
FUNCTION 0 = Connect MCLK to the 1.544MHz clock 1 = Open Switch 1.4 0 = Connect TCLK to the 1.544MHz clock 1 = Open Switch 1.3 0 = Connect RSYSCLK to the 1.544MHz clock 1 = Open Switch 1.2 0 = Connect TSYSCLK to the 1.544MHz clock 1 = Open Switch 1.1
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DS2155DK/DS2156DK T1/E1/J1 Single-Chip Transceiver Design Kit Daughter Cards
SWITCH2: PIN TO 2.048MHz (Offset = 0X0012) INITIAL VALUE = 0x3 (MSB) -- NAME MCLK TCLK RSYSCLK TSYSCLK (LSB) TSYSCLK
--
--
--
MCLK
TCLK
RSYSCLK
POSITION SWITCH2.3 SWITCH2.2 SWITCH2.1 SWITCH2.0
FUNCTION 0 = Connect MCLK to the 2.048MHz clock 1 = Open Switch 2.4 0 = Connect TCLK to the 2.048MHz clock 1 = Open Switch 2.3 0 = Connect RSYSCLK to the 2.048MHz clock 1 = Open Switch 2.2 0 = Connect TSYSCLK to the 2.048MHz clock 1 = Open Switch 2.1
SWITCH3: PIN-TO-PIN CONNECT (Offset = 0X0013) INITIAL VALUE = 0xF (MSB) -- NAME TSS_RS TCL_RC RSY_RC TSY_RC (LSB) TSY_RC
--
-- POSITION
--
TSS_RS
TCL_RC
RSY_RC
SWITCH3.3 SWITCH3.2 SWITCH3.1 SWITCH3.0
FUNCTION 0 = Connect TSSYNC to RSYNC 1 = Open Switch 3.4 0 = Connect TCLK to RCLK 1 = Open Switch 3.3 0 = Connect RSYSCLK to RCLK 1 = Open Switch 3.2 0 = Connect TSYSCLK to RCLK 1 = Open Switch 3.1
SWITCH4: PIN-TO-PIN CONNECT (Offset = 0X0014) INITIAL VALUE = 0x3 (MSB) -- NAME URCLK_2048 UTCLK_2048 RSER_TSER RSYNC_TSYNC (LSB) -- -- --
UTCLK_2048 UT_CLK_2048 RSER_TSER RSYNC_TSYNC
POSITION SWITCH4.3 SWITCH4.2 SWITCH4.1 SWITCH4.0
FUNCTION 0 = Connect UR_CLK (TSSYNC) to 2.048MHz 1 = Open Switch 4.4 0 = Connect UT_CLK (TCHCLK) to 2.048MHz 1 = Open Switch 4.3 0 = Connect RER to TSER 1 = Open Switch 4.2 0 = Connect RSYNC to TSYNC 1 = Open Switch 4.1
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LEVELS: SET LEVEL ON PIN (Offset = 0X0015) INITIAL VALUE = 0x6 (MSB) -- NAME -- BP_EN PPCTDM_EN TUSEL (LSB) TUSEL
--
-- POSITION LEVELS1.3 LEVELS1.2 LEVELS1.1 LEVELS1.0 --
--
--
BP_EN
PPCTDM_EN
FUNCTION
0 = Enable IDT switches that connect the UTOPIA bus to daughter card header 0 = Enable IDT switches that connect the TDM bus to the daughter card header 0 = Set DS2156.TUSEL to enable TDM backplane 1 = Set DS2156.TUSEL to enable UTOPIA backplane
Note: When the UTOPIA backplane is enabled (LEVELS.TUSEL = 1) there is a possibility for contention between the UTOPIA bus master and TSYSCLK, TSER, and RSER. To avoid this, the following switches should be opened when the UTOPIA backplane is enabled: SWITCH1.0, SWITCH2.0, SWITCH3.0, and SWITCH4.1
DS2155/DS2156 INFORMATION
For more information about the DS2155 and DS2156, please consult the DS2155 and DS2156 data sheets available on our website at www.maxim-ic.com/DS2155 and www.maxim-ic.comDS2156. Software downloads are also available for this design kit.
DS2155DK/DS2156DK INFORMATION
For more information about the DS2155DK and DS2156DK, including software downloads, please consult the DS2155DK/DS2156DK data sheet available on our website at www.maxim-ic.com/DS2155DK.
TECHNICAL SUPPORT
For additional technical support, please e-mail your questions to telecom.support@dalsemi.com.
SCHEMATICS
The DS2155DK/DS2156DK schematics are featured in the following 13 pages.
DOCUMENT REVISION HISTORY
REVISION DATE 032503 060303 012705 110106 DESCRIPTION Initial DS2155DK/DS2156DK data sheet release. Updated the Title, General Description, Features, and Basic Operation sections; "TIM" replaced with "daughter card." Updated schematics (removed component values for Fuse and Sidactor; see Component List). Updated schematics.
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Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c) 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor.
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DS2156, DS2155, DS2135Y DESIGN KIT
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TITLE:
DATE:
CONTENTS 1. COVER PAGE 2. SCT POPULATION OPTION (DS2155, DS2156, DS21352 OR DS21354) 3. TX AND RX ANALOG PATHS 4. TIM ADDRESS AND DATA BUS 5. CPLD ADDRESS DATA CONNECTIONS, BIAS LEVELS FOR SCT 6. UTOPIA: TIM HEADER AND BUS SWITCHES 7. TESTPOINTS FOR UTOPIA 2 8. UTOPIA: NETLIST ASSOCIATIONS 9. SWITCHING FOR CLOCKS AND TDM 10. SUPPLY DECOUPLING 11. SCT TESTPOINTS 12. NETLIST CROSS-REFERENCE 13. PART CROSS-REFERENCE
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82 RCLK 78 RLINK 98 RSYNC 92 RCHCLK 100RSYSCLK 79 RLCLK 85 RDATA 97 RFSYNC
U11
46 35 37 53 51 34 50 52 48 49
33 1 99 25 75 65 64 63 62 59 58 57 56 73 72 71 70 69 68 67 66 11 55 74 77
RCLK RLINK RSYNC RCHCLK RSYSCLK RLCLK RDATA RFSYNC
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TCLK TLINK TSYNC TCHCLK TSYSCLK TLCLK TDATA TSSYNC TSIG TESO
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RVDD TVDD DVDD1 DVDD2 DVDD3 DVDD4
TCLK TLINK TSYNC TCHCLK TSYSCLK TLCLK TDATA TSSYNC TSIG
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TCHBLK RCHBLK RLOS/LOTC INT* CS*
TCHBLK RCHBLK RLOS_LOTC INT CS
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RTIP RRING RPOSI RNEGI RCLKI RPOSO RNEGO RCLKO
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RTIP RRING RPOSI RNEGI RCLKI RPOSO RNEGO RCLKO
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8XCLK RCL LIUC
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8XCLK RCL LIUC
D/AD<7> D/AD<6> D/AD<5> D/AD<4> D/AD<3> D/AD<2> D/AD<1> D/AD<0>
D_AD7 D_AD6 D_AD5 D_AD4 D_AD3 D_AD2 D_AD1 D_AD0
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TTIP TRING TPOSI TNEGI TCLKI TPOSO TNEGO TCLKO
ALE/AS/A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
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TTIP TRING TPOSI TNEGI TCLKI TPOSO TNEGO TCLKO
A7 A6 A5 A4 A3 A2 A1 A0
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JTMS JTRST JTDI JTCLK JTDO
BTS MUX RD/DS* WR/RW*
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JTMS JTRST JTDI JTCLK JTDO
BTS MUX RD_DS WR_RW
NC3
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TVSS RVSS1 RVSS2 RVSS3 DVSS1 DVSS2 DVSS3 DVSS4
ESIBS<0> ESIBS<1>
UOP0 UOP1 UOP2 UOP3
RSER MCLK RMSYNC RSIG BPCLK TSTRST RSIGF XTALD ESIBRD TSER
N_P28
A
A
30 19 20 24 45 60 80 84
ESIBS0 36 ESIBS1 54
UOP0 UOP1 UOP2 UOP3
8 9 15 23
RSER 95 MCLK 21 RMSYNC 96 RSIG 94 BPCLK 3 TSTRST 14 RSIGF 93 XTALD 22 ESIBRD 76 TSER 47
TUSEL 26 N_P27 27
NC1 NC2
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RRING
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SW1 DPDT
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R60
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51.1
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C23
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0.1UF
61.9
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R54 61.9
49.9
49.9
Z8
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T1
R57
R56
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T1
R58
C7
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F3
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C24
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R T CONN_BANTAM_IPC
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L1
F4
1 2
J4
24 UH
RJ1
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Z
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1
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RJ48
C25
L1
F2
5 1 2
1
2 4
1
B
F1
2
5 2
R T CONN_BANTAM_IPC
J3
Z
R55
Z
C26
F6
1 1 2
CONN_BNC_5PIN J5
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Z
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TIM5V J8
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2 4 6 8 SNIM_B2 SNIM_B3 SNIM_B4 SNIM_B5 SNIM_B6 SNIM_B7 NIMD15 NIMD14 24 26 28 NIMD13 NIMD12
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(TIM LSB)
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PPC_RXCLK
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13 14 15 16 17 18 19 20
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PPC_TXCLK
A10 A11 17 19 21 23 CLK16384_T A14 A15 25 27 29 31 33 35 37 39 41 43 45 47 49 A12 A13 15
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A0 A1 A2 A3 A4 A5 A6 A7
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PPC_RXD PPC_TXD PPC_RSYNC PPC_TSYNC
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A9
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RW_T
UNUSED
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WE_T
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RESET_OUT
29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
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NIMD11 NIMD10 NIMD9 NIMD8
B
CS_T
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R1
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CLK1544_T
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INT
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D_AD0 D_AD1 D_AD2 D_AD3 D_AD4 D_AD5 D_AD6 D_AD7
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JX
J1X
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TP17 TP12 TP13
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10K
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R26
R25
10K
TUSEL
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CLK2048
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TP
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U5
V3_3
IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8 IO9 IO10 IO11 IO12 IO13 IO14 IO15
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IO72 IO71 IO70 IO69 IO68 IO67 IO66 IO65 IO64 IO63 IO62 IO61 IO60 IO59 IO58 IO57 IO56 IO55
GCK3 IO20
XILINX_XC9572XL
IO16
GCK1 IO17 GCK2 IO18
IO19
48 25 27 28 29
IO22 IO23 IO24 IO25 IO26 IO27 IO28 IO29 IO30 IO31 IO32 IO33 IO34 IO35 IO36
2.5V_3.3V1
26
TCK
45 97 96
IO21
2.5V_3.3V2
38
TDI
83
2.5V_3.3V3
51
TDO
TCK TDI TDO TMS
47 95 94 93 92 91 90 89 87 86 85 82 81 79 78 77
2.5V_3.3V4
88
TMS
3.3V1
5
NC<8-0>
3.3V2
57
1 3 4 6 8 9 10 11 12 13 14 15 16 17 18 20 22 23
U5
1
CLK16384_T
XILINX_XC9572XL
3.3V3
98
30 32 33 35 36 37 39 40 41 42 49 50 52 53
GND1
GND2
GND3
GND4
GND5
GND6
GND7
C
GND8
D_AD7 D_AD6 D_AD5 D_AD4 D_AD3 D_AD2 D_AD1 D_AD0
A11 A12
C
JT10
CONN_10P
21 31 44 62 69 75 84 100
1
1
2
2
BTS MUX WR_RW RD_DS A0 A1 A2 A3 A4 A5 A6 A7 DS17
V3_3
R52 330 R51 330
PPC_TDM_EN BP_EN WE_T
3
3
4
4
5
5
6
6
7
7
8
8
TDO TDI TMS TCK DS16 CS SW4_B0EN SW4_B1EN SW4_B2EN SW4_B3EN
IO54 IO53 IO52 IO51 IO50 IO49 IO48 IO47
9
9
10
10
RESET_OUT RW_T CS_T
B
IO46 IO45 IO44 IO43 IO42 IO41 IO40 IO39 IO38 IO37
B
1
1.0K
R24
2
1
R17
R13
V3_3
2 2 2 2 2 2 2 2 2
1
R15 R18 R29 R19 R37 R48 R32
1
R46 4.7K
1
2
1
2
R10
1
1
2
R6
SW1_B0EN SW1_B1EN SW1_B2EN SW1_B3EN SW2_B0EN SW2_B1EN SW2_B2EN SW2_B3EN SW3_B0EN SW3_B1EN SW3_B2EN SW3_B3EN
1
R38
2
1
76 74 72 71 70 68 67 66 65 64 63 61 60 59 58 56 55 54
1
1
V3_3
R40 330 R42 330 R36 330 R31 330 R39 330 R41 330 R35 330 R30 330 R45 330 R50 330 R43 330 R53 330
R8
1
R9
2
1
RED
1 2 2 1
1
R49
2
TSSYNC TLINK TSIG LIUC BTS INT RSYNC TSYNC TCLK
V3_3
1
1
2
2
1
1 1 1 1 1 1 1 1 1 1 1 1
R23
RLOS_LOTC_INDICATOR INT_INDICATOR INT RLOS_LOTC
A
R22
330
2
R16
1
GREEN LEDS
DS7 ..TO.. DS18
R11
DS2 RED
1
330
A
2 2 1
2
R47
1
DS3
2
R28
1
2
TP TP
R44
1
TP18 TP15 TP14
TITLE: DATE:
JTRST ESIBRD RPOSI RNEGI RCLKI TPOSI TNEGI TCLKI TSYSCLK TSTRST MUX RSYSCLK TSER
1 1
2
R61
1
TP
1
ALL UNMARKED BIAS RESISTORS ARE 10K
5 4 3
DS2156DK02A0
ENGINEER:
10/04/02 STEVE SCULLY
2 PAGE: 1
5 / 13
8
7
6
8 3 1
7
6
5
4
2
D
DS4 GREEN J7
1
R12 330
D
12
U4 IDTQS3R861
V3_3
1 2 2
GND
VCC
24
TIM J2X
GND VCC
12 1
NC1 BE* B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
U2 IDTQS3R861
V3_3
24 23 22 21 20 19 18 17 16 15 14 13
1 1
1 3 5 7 9
11 12
NC1
BE*
23
2 4 6 8 10
BP_EN
2 4 6 8 10 12 7 8 9 10 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 6 5 4 3 2 3
2
A0
B0
22
3
A1
B1
21
4 5 7 9 11 13
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A2
B2
20
GND
5
A3
B3
19
6
A4
B4
18
C
7
A5
B5
17
C
8
A6
B6
16
9 17
A7
B7
15
TXPRTY 15 GND
19 21 23 11
10
A8
B8
14
TXA_3_TXCLAV_2 TXA_1 TXDATA_6 TXDATA_4 TXDATA_2 TXDATA_0 TXSOC TXA_3_TXCLAV_2 TXCLAV_0 RXA_3_RXCLAV_2 GND
11
A9
B9
13
BP_EN TXA_4_TXCLAV_3 TXA_2_TXCLAV_1 TXA_0 TXDATA_7 TXDATA_5 TXDATA_3 TXDATA_1 TXENA R5 1 2 UT_CLK TXA_4_TXCLAV_3 51.1
GND
25 27 29
GND
12 1 2 3 4 5 6 7 8
U1 IDTQS3R861
GND VCC NC1 A0 A1 A2 A3 A4 A5 A6 BE* B0 B1 B2 B3 B4 B5 B6
V3_3
24 23 22 21 20 19 18 17 16 9 10 11 15
A7 A8 A9 B7 B8 B9
12 33 35 37 39
U3 IDTQS3R861
V3_3
GND
VCC
24
GND
31
B
1
NC1
BE*
23
BP_EN
B
2
A0
B0
22
3
A1
B1
21
4
A2
B2
20
5 43
A3
B3
19
RXPRTY 41 GND
45 47 49
6
A4
B4
18
7
A5
B5
17
GND
8
A6
B6
16
9
A7
B7
15
14 13
10
A8
B8
14
BP_EN TXA_2_TXCLAV_1 RXA_4_RXCLAV_3 RXA_2_RXCLAV_1 RXA_0 RXDATA_7 RXDATA_5 RXDATA_3 RXDATA_1 RXENA R4 1 2 UR_CLK
51.1
RXA_1 RXDATA_6 RXDATA_4 RXDATA_2 RXDATA_0 RXSOC RXA_3_RXCLAV_2 RXCLAV_0 RXA_2_RXCLAV_1 RXA_4_RXCLAV_3
11
A9
B9
13
A
BP_EN IS BIT MAPPED TO PLD ADDRESS 0X15 BIT 2 LOGIC 0 CLOSES SWITCHES
A
TITLE:
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
6 / 13
8
7
6
8 3 1
7
6
5
4
2
D
D
J2
J1
CONN_50P1
1
1 3 5 7 9
11 12
CONN_50P1
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50
TP TP
1 3
4 6 8 10
1
2
2 5 7 9 11 13
13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2
3
3
4
4
5
5
6
6
C
7
7
8
8
TXDATA_0 TXDATA_2 GND TXDATA_5 TXDATA_7 TXDATA_1 TXDATA_3 TXDATA_4 TXDATA_6 GND
C
RXDATA_0 RXDATA_2 GND RXDATA_5 RXDATA_7
9
9
10
10
RXDATA_1 RXDATA_3 RXDATA_4 RXDATA_6 GND
11 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49
11
12
12
13
13 14
14
15
15 16
16
1 1 1 1 1
1
TP TP
17
17 18
18
1
TP TP
19
19 20
20
1
TP TP
21
21 22
22
GND RXSOC
A10 A11 A12 A13 CLK16384_T CLK1544_T
CS_T
TP4 TP5 TP3 TP2
1 1
TP
TP11 TP10 TP9 TP8 TP6
TP
1
TP
A8 A9 RW_T WE_T
1
23
23 24
24
25
25 26
26
27
27 28
28
TXADDR0 GND TXADDR3 TXCLAV0
GND TXSOC TXADDR1 TXADDR2 TXADDR4 GND
TP1 TP16
TP
RESET_OUT
B
29
29 30
30
TP7 TP20 TP21
TP TP
B
31
31 32
32
33
34
33 34
35
1
1
1
35 36
36
TXENABLE 2 R14 1 UT_CLK
TP
TP22 GND
37
37 38
38
39
39 40
40
41
41 42
42
RXADDR1 GND RXADDR4
43
43 44
44
RXADDR0 RXADDR2 RXADDR3 RXCLAV0 GND
45
45 46
46
47
47 48
48
RXENB
UR_CLK 1
R21 51.1
2
49
49 50
50
A
ADTECH RX
ADTECH TX
A
TITLE:
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
7 / 13
8
7
6
8 3 1
7
6
5
4
2
RXADDR0 UR_ADDR0 RXENB UR_ENB TXDATA_6 UT_DATA6 TXDATA_6 TSIG RXSOC UR_SOC TXADDR0 UT_ADDR0 TXDATA_7 UT_DATA7 TXADDR1 UT_ADDR1 TXADDR2 UT_ADDR2 TXA_2_TXCLAV_1 TLCLK TXA_3_TXCLAV_2 TLINK TXA_4_TXCLAV_3 TPOSI UT_CLAV LIUC TXENABLE UT_ENB TXENA UOP1 TXADDR3 UT_ADDR3 TXADDR4 UT_ADDR4 TXCLAV0 TXCLAV_0 TXA_1 TCHBLK TXA_0 UOP3 RXSOC RCHBLK RXENA BPCLK
RXA_0 RCHCLK
D
RXADDR1 UR_ADDR1
RXA_1 RSIGF
D
RXADDR2 UR_ADDR2
RXA_2_RXCLAV_1 RSIG
RXADDR3 UR_ADDR3
RXA_3_RXCLAV_2 RMSYNC
TXDATA_7 TSYSCLK
RXADDR4 UR_ADDR4
RXA_4_RXCLAV_3 RFSYNC
C
RXCLAV0 UR_CLAV
RXCLAV_0 RSER
C
RXDATA_0 UR_DATA0
RXDATA_0 RLINK
RXDATA_1 UR_DATA1 TXDATA_0 UT_DATA0 TXDATA_1 UT_DATA1 TXDATA_2 UT_DATA2 TXDATA_3 UT_DATA3 TXDATA_3 TNEGO TXDATA_2 TCLKO TXDATA_1 TCLKI TXDATA_0 TNEGI
RXDATA_1 RLCLK
TXSOC UT_SOC
TXSOC UOP0
B
B
RXDATA_2 UR_DATA2
RXDATA_2 RPOSI
RXDATA_3 UR_DATA3
RXDATA_3 RNEGI
RXDATA_4 UR_DATA4
RXDATA_4 RCLKI
UT_CLK UR_CLK
TSSYNC TCHCLK
2
R33
RXDATA_5 UR_DATA5
RXDATA_5 RCLKO
11
C13
RXDATA_6 UR_DATA6 TXDATA_4 UT_DATA4 TXDATA_5 UT_DATA5
RXDATA_6 RNEGO
2
0.1UF NOPOP R34 C14
TXDATA_4 TPOSO TXDATA_5 TSER
TITLE:
RXDATA_7 UR_DATA7
RXDATA_7 RPOSO
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
2
8 / 13
8
7
6
0.1UF NOPOP
A
11
2
A
8 3 1
7
6
5
4
2
D V3_3
16 12 15 4 7 10 13 9 1
NC1 VCC 3OE* 4OE* 1Y 2Y 3Y 4Y NC2 1OE* 2OE* 1A 2A 3A 4A GND
U8 IDTQS3125 U7 IDTQS3125
V3_3
D
1
NC1
VCC
16
1OE*
3OE*
12
2OE*
4OE*
15
SW1_B0EN 2 SW1_B1EN 5 CLK1544_T 3
1A
1Y
4
6
2A
2Y
7
11
3A
3Y
10
14 8
4A
4Y
13
SW1_B2EN SW1_B3EN TSYSCLK RSYSCLK TCLK MCLK SW3_B0EN 2 SW3_B1EN 5 3 TSYSCLK 6 RSYSCLK 11 TCLK 14 TSSYNC SW3_B2EN SW3_B3EN RCLK RCLK RCLK RSYNC
8
GND
NC2
9
C
SWITCH 1 IS MEMORY MAPPED TO PLD REGISTER 0X11 LOGIC 0 CLOSES SWITCH LOGIC 1 OPENS SWITCH
SWITCH 3 IS MEMORY MAPPED TO PLD REGISTER 0X13 LOGIC 0 CLOSES SWITCH LOGIC 1 OPENS SWITCH
C
U10 IDTQS3125
V3_3
1
1
NC1
VCC
16
U9 IDTQS3125
NC1 1OE* 2OE* 1A 2A 3A VCC 3OE* 4OE* 1Y 2Y 3Y
V3_3
16 12 15 4 7 10 14 8
4A GND 4Y NC2
2
1OE*
3OE*
12
5
2OE*
4OE*
15
SW2_B0EN SW2_B1EN CLK2048
3
1A
1Y
4
B
6
2A
2Y
7
B
11
3A
3Y
10
14
4A
4Y
13
SW2_B2EN SW2_B3EN TSYSCLK RSYSCLK TCLK MCLK GREEN DS1
12
GND VCC
SW4_B0EN 2 SW4_B1EN 5 3 RSYNC 6 RSER CLK2048 11
8
GND
NC2
9
13 9
SW4_B2EN SW4_B3EN TSYNC TSER UT_CLK UR_CLK
U6 IDTQS3R861
V3_3
24 23 22 21 20 19 18 17 16
B6 B7 B8 B9
1
2
1
SWITCH 2 IS MEMORY MAPPED TO PLD REGISTER 0X12 LOGIC 0 CLOSES SWITCH LOGIC 1 OPENS SWITCH
1
NC1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B5 B4 B3 B2 B1 B0 BE*
R7 330
2
2 3 4 5 6 7 8 9 10 11
SWITCH 4 IS MEMORY MAPPED TO PLD REGISTER 0X14 LOGIC 0 CLOSES SWITCH LOGIC 1 OPENS SWITCH
A
TSER RSER TCLK RCLK TSYNC RSYNC
15 14 13
PPC_TDM_EN PPC_TXD PPC_RXD PPC_TXCLK PPC_RXCLK PPC_TSYNC PPC_RSYNC
A
PPC_TDM_EN IS BIT MAPPED TO PLD ADDRESS 0X15 BIT 1 LOGIC 0 CLOSES SWITCHES
TITLE:
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
9 / 13
8
7
6
A
C
D
B
TP33 TP38 TP37 TP36 TP35 TP34 TP32 TP31
TP24 TP25 TP26 TP27 TP28 TP29 TP23 TP30
8
TP
8
TP
1
1
TP
TP
1
1
TP
TP
1
1
TP
TP
1
7
1
7
TP
TP
1
1
TP
TP
1
1
TP
TP
1
1
TP
TP
1
6
1
C35
2
10UF C36
1
6
V3_3
1
1UF C31
2
2 2 2 2
5
0.1UF C1 C32 0.1UF C33 0.1UF 0.1UF C34
1 1 1 1
5
2
0.1UF C22
1
2
0.1UF C29
1 1
C30 0.1UF 0.1UF C11
2 2 2
0.1UF C10
1
4
1 1
C9 0.1UF 0.1UF C8
4 3 ENGINEER: TITLE:
2 2 2 2 2
0.1UF C18 C16 0.1UF 0.1UF C15
1 1 1 1
3
2 2 2 2 2 2 2 2 2
C12 0.1UF C21 0.1UF 0.1UF C3 0.1UF 0.1UF C17 C4 0.1UF 0.1UF C5 C19 0.1UF 0.1UF C2
1 1 1 1 1 1
2
STEVE SCULLY
PAGE:
DS2156DK02A0
2 1
1 1 1
V3_3
DATE:
1
VCC
10/04/02
10 / 13
A
C
D
B
8 3 1
7
6
5
4
2
D
V3_3
D
RCLK RLINK RSYNC RCHCLK RSYSCLK RLCLK RDATA RFSYNC
46 35 37 53 51 34 50 52 48 49
18 31 44 61 81 83
1
33 1 99 25 75 65 64 63 62 59 58 57 56 73 72 71 70 69 68 67 66 11 55 74 77
RCLK RLINK RSYNC RCHCLK RSYSCLK RLCLK RDATA RFSYNC
17
86
87
TCLK TLINK TSYNC TCHCLK TSYSCLK TLCLK TDATA TSSYNC TSIG TESO
16
RVDD TVDD DVDD1 DVDD2 DVDD3 DVDD4
82 78 98 92 100 79 85 97
TCLK TLINK TSYNC TCHCLK TSYSCLK TLCLK TDATA TSSYNC TSIG
VALUE=NA
TCHBLK RCHBLK RLOS/LOTC INT* CS*
TCHBLK RCHBLK RLOS_LOTC INT CS
C
88
C
91
90
DS2156 TQFP
RTIP RRING RPOSI RNEGI RCLKI RPOSO RNEGO RCLKO
89
RTIP RRING RPOSI RNEGI RCLKI RPOSO RNEGO RCLKO
13
6
8XCLK RCL LIUC
12
8XCLK RCL LIUC
D/AD<7> D/AD<6> D/AD<5> D/AD<4> D/AD<3> D/AD<2> D/AD<1> D/AD<0>
D_AD7 D_AD6 D_AD5 D_AD4 D_AD3 D_AD2 D_AD1 D_AD0
29
32
38
B
39
B
40
43
42
TTIP TRING TPOSI TNEGI TCLKI TPOSO TNEGO TCLKO
ALE/AS/A<7> A<6> A<5> A<4> A<3> A<2> A<1> A<0>
41
TTIP TRING TPOSI TNEGI TCLKI TPOSO TNEGO TCLKO
A7 A6 A5 A4 A3 A2 A1 A0
2
5
7
4
JTMS JTRST JTDI JTCLK JTDO
10
JTMS JTRST JTDI JTCLK JTDO
BTS MUX RD/DS* WR/RW* NC3
BTS MUX RD_DS WR_RW
28
N_P28
TVSS RVSS1 RVSS2 RVSS3 DVSS1 DVSS2 DVSS3 DVSS4
ESIBS<0> ESIBS<1>
UOP0 UOP1 UOP2 UOP3
RSER MCLK RMSYNC RSIG BPCLK TSTRST RSIGF XTALD ESIBRD TSER
30 19 20 24 45 60 80 84
ESIBS0 36 ESIBS154
UOP0 UOP1 UOP2 UOP3
8 9 15 23
RSER 95 MCLK 21 RMSYNC 96 RSIG 94 BPCLK 3 TSTRST 14 RSIGF 93 XTALD 22 ESIBRD 76 TSER 47
TUSEL 26 N_P27 27
NC1 NC2
A
A
TITLE:
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
11 / 13
8
7
6
8 3 1
7
6
5
4
2
*** Signal Cross-Reference for the entire design ***
WR_RW XTALD
5C4<> 2A3< 11A3< 2A5> 11A4>
D
TNEGI TNEGO TPOSI TPOSO TRING TSER TSIG TSSYNC TSTRST TSYNC TSYSCLK
D
C
C
B
B
A
8XCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BPCLK BP_EN BTS CLK1544_T CLK2048 CLK16384_T CS CS_T D_AD0 D_AD1 D_AD2 D_AD3 D_AD4 D_AD5 D_AD6 D_AD7 ESIBRD ESIBS0 ESIBS1 INT INT_INDICATOR JTCLK JTDI JTDO JTMS JTRST LIUC MCLK MUX NIMD8 NIMD9 NIMD10 NIMD11 NIMD12 NIMD13 NIMD14 NIMD15 N_P27 N_P28 PPC_RSYNC PPC_RXCLK PPC_RXD PPC_TDM_EN PPC_TSYNC PPC_TXCLK PPC_TXD RCHBLK RCHCLK RCL RCLK
2C8> 11C7> 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 5C4<> 2B3< 11B3< 4C6<> 7B1<> 4B6<> 7B1<> 4C3<> 7C3<> 4C3<> 5C1<> 7C3<> 4C3<> 5C1<> 7B3<> 4B3<> 7B3<> 4B3<> 4B3<> 2A5> 8D4> 11A4> 5C1<> 6B2< 6B6< 6C2< 6C6< 5D4<> 2B3< 5A6< 11A3< 7B3<> 9D8<> 4B2< 5D3<> 9B3<> 9B8<> 4B4<> 5D3<> 7B3<> 5B4<> 2C3< 11C3< 4B8<> 5B1<> 7B3<> 2B3<> 4B6<> 5C1<> 11B3<> 2C3<> 4B6<> 5C1<> 11B3<> 2C3<> 4B6<> 5C1<> 11C3<> 2C3<> 4B6<> 5C1<> 11C3<> 2C3<> 4B6<> 5C1<> 11C3<> 2C3<> 4B6<> 5C1<> 11C3<> 2C3<> 4A6<> 5C1<> 11C3<> 2C3<> 4A6<> 5D1<> 11C3<> 2A5<> 11A4<> 5A8< 2A6<> 11A6<> 2A6<> 11A5<> 2C3> 4A8<> 5A2<> 11C3> 5A6< 5A2<> 2A8< 11A7< 2A8< 11A7< 2A8> 11A7> 2B8< 11B7< 2B8< 5A8< 11A7< 8B4> 2C8< 5A6< 11B7< 9B6<> 9C6<> 2A5< 11A5< 5C4<> 2A3< 5A8< 11A3< 4B2<> 4B2<> 4B2<> 4B2<> 4B2<> 4B2<> 4B2<> 4C2<> 2A4< 11A4< 2A3< 11A3< 4C8<> 9A4<> 4C8<> 9A4<> 4C8<> 9A4<> 5C1<> 9A4< 4B8<> 9A4<> 4C8<> 9A4<> 4C8<> 9A4<> 2C3> 8D4> 11C3> 2D6> 8D7> 11D5> 2C8> 11C7> 2D6> 9A6<> 9C1<> 9C1<> 9D1<> 11D6>
A
RCLKI RCLKO RDATA RD_DS RESET_OUT RFSYNC RLCLK
8A7> 2C8< 5A8< 11C7< 2C8> 8A7> 11C7> 2D6> 11D5> 5C4<> 2A3< 11A3< 4B6<> 5B1<> 7B1<> 2D6> 8C7> 11D5> 2D6> 8B7> 11D5>
RLINK 2D6> 8B7> 11D6> RLOS_LOTC 2C3> 5B2<> 11C3> RLOS_LOTC_INDICATOR 5A2<> RMSYNC 2A5> 8C7> 11A5> RNEGI 8B7> 2C8< 5A8< 11C7< RNEGO 2C8> 8A7> 11C7> RPOSI 8B7> 2C8< 5A8< 11C7< RPOSO 2C8> 8A7> 11C7> RRING 2C8< 3B8< 11C7< RSER 2A5> 8C7> 9A6<> 9B3<> 11A5> RSIG 2A5> 8D7> 11A5> RSIGF 2A5> 8D7> 11A4> RSYNC 2D6<> 9A6<> 9B3<> 9C1<> 11D5<> 5A6< RSYSCLK 9B6<> 9C3<> 9D6<> 2D6< 5A8< 11D5< RTIP 2C8< 3B8< 11C7< RW_T 4B6<> 5B1<> 7B1<> RXADDR0 7B8<> 8D8 RXADDR1 7B6<> 8D8 RXADDR2 7B8<> 8D8 RXADDR3 7B8<> 8C8 RXADDR4 7B6<> 8C8 RXA_0 6B2<> 8D7> RXA_1 6B7<> 8D7> RXA_2_RXCLAV_1 6A7<> 6B2<> 8D7> RXA_3_RXCLAV_2 6A7<> 6C7<> 8C7> RXA_4_RXCLAV_3 6A7<> 6B2<> 8C7> RXCLAV0 7A8<> 8C8 RXCLAV_0 6A7<> 8C7> RXDATA_0 6B7<> 7C8<> 8B7> 8B8 RXDATA_1 6A2<> 7C6<> 8B7> 8B8 RXDATA_2 6B7<> 7C8<> 8B7> 8B8 RXDATA_3 6B2<> 7C6<> 8B7> 8B8 RXDATA_4 6B7<> 7C6<> 8A7> 8A8 RXDATA_5 6B2<> 7C8<> 8A7> 8A8 RXDATA_6 6B7<> 7C6<> 8A7> 8A8 RXDATA_7 6B2<> 7C8<> 8A7> 8A8 RXENA 6A2<> 8D4> RXENB 7A6<> 8D5 RXPRTY 6B5<> RXSOC 6B7<> 7B6<> 8D4> 8D5 SNIM_B2 4C2<> SNIM_B3 4C2<> SNIM_B4 4C2<> SNIM_B5 4C2<> SNIM_B6 4C2<> SNIM_B7 4C2<> SW1_B0EN 5A4<> 9D8< SW1_B1EN 5A4<> 9D8< SW1_B2EN 5A3<> 9D6< SW1_B3EN 5A3<> 9D6< SW2_B0EN 5A3<> 9B8< SW2_B1EN 5A3<> 9B8< SW2_B2EN 5A3<> 9B6< SW2_B3EN 5A3<> 9B6< SW3_B0EN 5A3<> 9D3< SW3_B1EN 5A3<> 9D3< SW3_B2EN 5A3<> 9D1< SW3_B3EN 5A3<> 9D1< SW4_B0EN 5B4<> 9B3< SW4_B1EN 5B4<> 9B3< SW4_B2EN 5B4<> 9B2< SW4_B3EN 5B4<> 9B2< TCHBLK 2D3> 8C4> 11C3> TCHCLK 2D5> 11D4> 8A1< TCK 5B8<> 5D8< TCLK 9A6<> 9B6<> 9C3<> 9C6<> 2D5< 5A6< 11D5< TCLKI 8B4> 2B8< 5A8< 11B7< TCLKO 2B8> 8A4> 11B7> TDATA 2D5<> 11D4<> TDI 5B8<> 5D7< TDO 5B8<> 5C7< TIM5V 4D3<> 4D8<> TLCLK 2D5> 8C4> 11D4> TLINK 8C4> 2D5< 5B6< 11D5< TMS 5B8<> 5C7< 8B4> 2B8< 5A8< 11B7< 2B8> 8A4> 11B7> 8C4> 2B8< 5A8< 11B7< 2B8> 8A4> 11B7> 2B8> 11B7> 3C8< 8A4> 9A6<> 9B2<> 2A5< 5A8< 11A4< 8D1> 2D5< 5B6< 11D4< 9C3<> 2D5< 5B6< 8A1< 11D4< 2A5< 5A8< 11A4< 2D5<> 9A6<> 9B2<> 11D5<> 5A6< 8D1> 9B6<> 9D3<> 9D6<> 2D5< 5A8< 11D4< TTIP 2B8> 11B7> 3C8< TUSEL 5D2<> 2A4< 11A4< TXADDR0 7B5<> 8D5 TXADDR1 7B4<> 8C5 TXADDR2 7B4<> 8C5 TXADDR3 7B5<> 8C5 TXADDR4 7B4<> 8C5 TXA_0 6C2<> 8D4> TXA_1 6C7<> 8C4> TXA_2_TXCLAV_1 6B2<> 6C2<> 8C4> TXA_3_TXCLAV_2 6C7<> 6C7<> 8C4> TXA_4_TXCLAV_3 6C2<> 6C2<> 8C4> TXCLAV0 7B5<> 8B5 TXCLAV_0 6C7<> 8B5 TXDATA_0 6C7<> 7C5<> 8B4> 8B5 TXDATA_1 6C2<> 7C4<> 8B4> 8B5 TXDATA_2 6C7<> 7C5<> 8A4> 8A5 TXDATA_3 6C2<> 7C4<> 8A4> 8A5 TXDATA_4 6C7<> 7C4<> 8A4> 8A5 TXDATA_5 6C2<> 7C5<> 8A4> 8A5 TXDATA_6 6C7<> 7C4<> 8D1> 8D2 TXDATA_7 6C2<> 7C5<> 8D1> 8D2 TXENA 6C2<> 8C1> TXENABLE 7B4<> 8C2 TXPRTY 6C5<> TXSOC 6C7<> 7B4<> 8B1> 8B2 UOP0 2A6> 8B1> 11A5> UOP1 2A6> 8C1> 11A5> UOP2 2A6> 11A5> UOP3 2A6> 8D4> 11A5> UR_ADDR0 8D8 UR_ADDR1 8D8 UR_ADDR2 8D8 UR_ADDR3 8C8 UR_ADDR4 8C8 UR_CLAV 8C8 UR_CLK 9B2<> 6A1< 7A8< 8A2< UR_DATA0 8B8 UR_DATA1 8B8 UR_DATA2 8B8 UR_DATA3 8B8 UR_DATA4 8A8 UR_DATA5 8A8 UR_DATA6 8A8 UR_DATA7 8A8 UR_ENB 8D5 UR_SOC 8D5 UT_ADDR0 8D5 UT_ADDR1 8C5 UT_ADDR2 8C5 UT_ADDR3 8C5 UT_ADDR4 8C5 UT_CLAV 8B4> UT_CLK 9B2<> 6C1< 7B4< 8A2< UT_DATA0 8B5 UT_DATA1 8B5 UT_DATA2 8A5 UT_DATA3 8A5 UT_DATA4 8A5 UT_DATA5 8A5 UT_DATA6 8D2 UT_DATA7 8D2 UT_ENB 8C2 UT_SOC 8B2 WE_T 4B6<> 5B1<> 7B1<>
TITLE:
DATE:
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
12 / 13
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*** Part Cross-Reference for the entire design ***
D
D
C
TP22 TP23 TP24 TP25 TP26 TP27 TP28 TP29 TP30 TP31 TP32 TP33 TP34 TP35 TP36 TP37 TP38 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 Z1 Z2 Z3 Z4 Z5 Z6 Z7 Z8 Z9 Z10
TSTPNT_SNG 7B1 TSTPNT_SNG 10A7 TSTPNT_SNG 10A8 TSTPNT_SNG 10A7 TSTPNT_SNG 10A7 TSTPNT_SNG 10A7 TSTPNT_SNG 10A7 TSTPNT_SNG 10A7 TSTPNT_SNG 10A7 TSTPNT_SNG 10A4 TSTPNT_SNG 10A4 TSTPNT_SNG 10A5 TSTPNT_SNG 10A5 TSTPNT_SNG 10A5 TSTPNT_SNG 10A5 TSTPNT_SNG 10A5 TSTPNT_SNG 10A5 IDTQS3R861_U 6B3 IDTQS3R861_U 6D3 IDTQS3R861_U 6B6 IDTQS3R861_U 6D6 XILINX_XC9572XL 5D4 5D7 IDTQS3R861_U 9B5 IDTQS3125_U 9D3 IDTQS3125_U 9D7 IDTQS3125_U 9B3 IDTQS3125_U 9B7 DS2156_TQFP 2D7 SIDACTOR_2 3C4 SIDACTOR_2 3D5 SIDACTOR_2 3A5 SIDACTOR_2 3B5 SIDACTOR_2 3C6 SIDACTOR_2 3A4 SIDACTOR_2 3C4 SIDACTOR_2 3A4 SIDACTOR_2 3C4 SIDACTOR_2 3B4
C
B
B
A
A
TITLE:
DATE:
1 C1 C2 C3 C4 C5 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C21 C22 C23 C24 C25 C26 C27 C29 C30 C31 C32 C33 C34 C35 C36 DS1 DS2 DS3 DS4 DS5 DS6 DS7 DS8 DS9 DS10 DS11 DS12 DS13 DS14 DS15 DS16 DS17 DS18 F1 F2 F3 F4 F5 F6 J1 J2 J3 J4 J5 J6 J7 J8 J9 JT10 L1 R1 R2 R3 R4 R5 R6
DS2156_TQFP 11D7 CAP 10B5 CAP 10B3 CAP 10B2 CAP 10B2 CAP 10B2 CAP 3D6 CAP 10B4 CAP 10B4 CAP 10B4 CAP 10B4 CAP 10B2 CAP 8A1 CAP 8A1 CAP 10B3 CAP 10B3 CAP 10B2 CAP 10B3 CAP 10B3 CAP 10B2 CAP 10B5 CAP 3A6 CAP 3C5 CAP 3B5 CAP 3A5 CAP 3D5 CAP 10B4 CAP 10B4 CAP 10B6 CAP 10B5 CAP 10B5 CAP 10B5 CAP 10B6 CAP 10B6 LED 9B4 LED 5A2 LED 5A2 LED 6D5 LED 5A3 LED 5A4 LED 5A3 LED 5A4 LED 5A4 LED 5A3 LED 5A4 LED 5A3 LED 5A3 LED 5A3 LED 5A3 LED 5B5 LED 5B5 LED 5A3 FUSE 3B4 FUSE 3B4 FUSE 3D4 FUSE 3C4 FUSE 3D4 FUSE 3A3 CONN_50P1 7D5 CONN_50P1 7D7 CONN_BANTAM_IPC 3B1 CONN_BANTAM_IPC 3C1 CONN_BNC_5PIN 3A3 CONN_BNC_5PIN 3D2 CONN_50P2 6D4 CONN_50P2 4D3 CONN_50P2 4D7 CONN_10P 5C8 CHOKE_DUAL_T1 3B4 3C4 RES1 4B2 RES 3B7 RES 3B7 RES 6A2 RES 6C2 RES1 5A7
R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R38 R39 R40 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 RJ1 SW1 T1 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 TP12 TP13 TP14 TP15 TP16 TP17 TP18 TP20 TP21
RES 9B4 RES1 5A2 RES1 5A7 RES1 5A7 RES1 5A2 RES 6D5 RES1 5B6 RES1 7B4 RES1 5B6 RES1 5A7 RES1 5B6 RES1 5A6 RES1 5A6 RES1 7A8 RES1 5A7 RES1 5A7 RES1 5B8 RES1 5D7 RES1 5D8 RES1 5D8 RES1 5A7 RES1 5A6 RES 5A3 RES 5A3 RES1 5A6 RES1 8A1 RES1 8A1 RES 5A3 RES 5A3 RES1 5A6 RES 5A7 RES 5A3 RES 5A4 RES 5A3 RES 5A4 RES 5A3 RES1 5A7 RES 5A3 RES1 5B7 RES1 5A7 RES1 5A6 RES1 5A7 RES 5A3 RES 5B4 RES 5B4 RES 5A3 RES1 3B6 RES1 3B6 RES 3B5 RES 3B6 RES 3D7 RES 3C7 RES 3A5 RES1 5A7 RJ48_CON 3C3 SWITCH_DPDT_SLIDE_6P 3A6 XFMR_2IN_4OUT_U 3B5 3D5 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7C2 TSTPNT_SNG 7C2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 7B2 TSTPNT_SNG 5D2 TSTPNT_SNG 5D2 TSTPNT_SNG 5A6 TSTPNT_SNG 5A6 TSTPNT_SNG 7B2 TSTPNT_SNG 5D2 TSTPNT_SNG 5A6 TSTPNT_SNG 7B2 TSTPNT_SNG 7B1
DS2156DK02A0
ENGINEER: 5 4 3
10/04/02 STEVE SCULLY
2 PAGE: 1
13 / 13
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